1. Field of the Invention
This invention relates generally to synchronous semiconductor memory devices driven in response to exterior system clocks, and more particularly, to digital delay locked loops which can reduce the power consumption of such synchronous semiconductor memory devices.
2. Description of the Related Art
A synchronous semiconductor memory device typically has a buffer for receiving an exterior system clock and generating an internal clock which is used in the interior of the chip to perform high-speed operations. Therefore, each device within the chip that receives the output from the buffer operates in synchronization with the system clock. However, since the buffer delays the system clock, a phase difference occurs between the external system clock and the internal clock. That is, the operation of the interior of the chip is delayed with respect to the external clock by this phase difference. Therefore, efforts have been made to devise a technique for operating the internal clock in complete synchronization with the external system clock.
One prior art method for eliminating the phase delay uses a phase locked loop (PLL), a delay locked loop (DLL), or other similar device to minimize the skew between the external system clock and the internal clock. However, this technique is not suitable for use with high-speed synchronous DRAM (Dynamic Random Access Memory) devices due to the long locking time for phase synchronization. This technique also increases the standby current consumed by the device while it is in a standby state. Furthermore, there are difficulties in operating a PLL or DLL at specific frequencies.
FIG. 1 shows another prior art scheme for reducing the skew between the external system clock and the internal clock in which a digital delay locked loop using a synchronous delay line (SDL) generates an internal clock which is accurately synchronized with the external system clock.
Referring to FIG. 1, a delay buffer BDC delays an external system clock CLK. A first clock PCLK_M generated by the delay buffer BDC is connected to the input node of a main delayer MDC, the input nodes of a plurality of phase delay detectors DDC1-DDCn, and the input node of a second synchronous delay line consisting of a plurality of unit delayers BUD1-BUDn. The output node of the main delayer MDC is connected to a plurality of unit delayers FUD1-FUDn each having the same delay length. The plurality of unit delayers FUD1-FUDn are connected to each other in series and form a first synchronous delay line. The plurality of unit delayers FUD1-FUDn within the first synchronous delay line delays a second clock D1, which is output from the main delayer MDC, and generates delayed clocks D2-Dn.
In the second synchronous delay line, the unit delayers BUD1-BUDn each have the same delay length as the unit delayers FUDi, where i=1 . . . n, and are serially connected. Switches SWC1-SWCn are connected between the input and output nodes of the unit delayers BUD1-BUDn and are arranged to selectively supply either the first clock PCLK_M or one of the a delayed clocks D2'-Dn' to an output node as the internal clock signal PCLK in response to the activation one of a plurality of enable signals Fi which are output by the phase delay detectors DDCi where i=1 . . . n. The switches SWC1-SWCn receive, through their respective input terminals, the first clock PCLK_M and the delayed clocks Di' generated by the unit delayers BUD1-BUDn of the second synchronous delay line, and are individually enabled by the activation of output signals from the phase delay detectors DDC1-DDCn. The phase delay detectors DDC1-DDCn latch the delayed clocks D1-Dn when the first clock PCLK_M switches to logic "LOW" and activate the enable signal Fi when PCLK_M is phase-synchronized with the delayed clock Di.
An example of the operation of FIG. 1 will now be described with reference to FIG. 2 which is a timing chart showing waveforms of various signals in the circuit of FIG. 1. If the external system clock CLK shown in FIG. 2 is applied, the delay buffer BDC generates the first clock PCLK_M which is delayed and level-converted to a clock pulse shown in FIG. 2. The first clock PCLK_M is delayed by the main delay MDC having a delay length corresponding to the delay length of the delay buffer BDC and generated as the second clock D1. Moreover, the first clock PCLK_M generated by the delay buffer BDC is simultaneously supplied to the first input nodes of each of the phase delay detectors DDC1-DDCn and to the unit delayer BUD1 of the second synchronous delay line. The second clock D1 is sequentially delayed by the unit delayers FUD1-FUDn of the first synchronous delay line, which are serially connected to the output node of the main delayer MDC, and generated as delayed clocks D2-Dn. Each of the unit delayers FUD1-FUDn has the same delay length. The second clock D1 generated by the main delayer MDC and the delayed clocks D2-Dn are supplied to the second input nodes of each of the phase delay detectors DDC1-DDCn.
The phase delay detector DDC1 compares the phase of the first clock PCLK_M generated by the delay buffer BDC with the phase of the second clock D1 generated by the main delayer MDC. Other phase delay detectors DDC2-DDCn compare the phase of the first clock PCLK_M generated by the delay buffer BDC with the phase of each of the delayed clocks D2-Dn generated at respective output nodes of the unit delayers FUD1-FUDn of the first synchronous delay line. The phase delay detectors DDC1-DDCn activate the enable signal Fi that has the same period as the delayed clock Di when the two clocks are phase-synchronized.
For example, if the first clock PCLK_M has the same phase as a delayed clock D12 generated by unit delayer FUD12, phase delay detector DDC12 latches the delayed clock D12 and generates an enable signal during a logic "LOW" interval of the first clock PCLK_M. That is, the phase delay detector DDC12 activates the output signal F12 as indicated by waveform F12 shown in FIG. 2. Therefore, switch SWC12, which has a control terminal connected to the output node of the phase delay detector DDC12, is turned on, and a clock D12' sequentially delayed by the unit delayers BUD1-BUD11 is connected to the output node of the internal clock PCLK. In other words, by enabling the signal F12 from the phase delay detector DDC12, the circuit of FIG. 1 generates the internal clock from the output D12' by delaying the first clock PCLK_M through the unit delayers BUD1-BUD11. In this case, the internal clock PCLK has no delay generated by the main delayer MDC.
The internal clock PCLK generated by the above-described operation is generated with the same phase as the external system clock CLK without any delay after two periods of the external system clock CLK. Since it takes a short time to equalize the phase between the external system clock CLK and the internal clock PCLK, the performance of a synchronous memory device can be improved by using a digital delay locked loop that has a synchronous delay line as shown in FIG. 1.
The detailed construction of the digital delay locked loop of FIG. 1 will now be described with reference to FIG. 3 so that the preferred embodiments of the present invention, which will be described later on, can be more fully understood. FIG. 3 is a circuit diagram showing more details of the unit delayers FUDD1-FUDn and BUD1-BUDn constituting the first and second synchronous delay lines, the switches SWC1-SWCn, the phase delay detectors DDC2-DDCn, and the mutual connection relationship therebetween, of the digital delay locked loop of FIG. 1.
The delay buffer BDC indicated in FIG. 1 is not shown in FIG. 3. Also, the phase delay detector DDC1 for receiving the second clock D1 generated by the main delayer MDC is also shown. Instead of the phase delay detector DDC1, a bypass circuit BP is included in order to accommodate situations in which the synchronization through the synchronous delay line is not correct. The bypass circuit BP receives a carry output from the phase delay detector DDCn, and if the period of the external system clock CLK is longer than the delay time of the synchronous delay line, the bypass circuit BP bypasses the first clock PCLK_M directly to the internal clock PCLK by the operation of switch SWC1.
An internal delayer ID having two inverters connected in series is included as a final output stage in order to accurately detect the level and output time of the internal clock PCLK. The phase delay detectors DDC2-DDCn have the same internal construction and consist of transmission switches S1 and S2 coupled by a PMOS transistor and an NMOS transistor, inverters I1 and I2 arranged to form a latch, inverters I3 and I4 arranged to form a latch, inverters I5 and I6, and NAND gates N1 and N2.
FIG. 4 is a timing chart illustrating the operation of the circuit of FIG. 3. When the external system clock CLK is applied, the first clock PCLK_M delayed by the delay buffer BDC appears at an input node N1. The main delay MDC delays the first clock PCLK_M by the delay length produced by four inverters and generates the second clock D1. The first clock PCLK_M is sequentially delayed by the serially connected unit delayers BUD1-BUDn of the second synchronous delay line, and the delayed clocks D2'-Dn' are generated at the respective output nodes of the unit delayers BUD1-BUDn, as shown in FIG. 4. The delayed clocks D1'-Dn' are advanced relative to the clocks D1-Dn by the delay length of the main delayer MDC. When one of the enable signals is activated, one of the switches SWC1-SWCn is turned on, thereby selecting only one of the delayed clocks D1'-Dn' to be provided as the internal clock PCLK.
The second clock D1 generated by the main delayer MDC is sequentially delayed by the unit delayers FUD1-FUDn, each of which has two inverters serially connected and which generate the delayed clocks D2-D14 as shown in FIG. 4. The clocks D2-Dn generated at the output nodes of the unit delays FUD1-FUDn are supplied to each transmission switch S1 of the phase delay detectors DDC2-DDCn. Each transmission switch S1 within the phase delay detectors DDC2-DDCn includes one NMOS transistor and one PMOS transistor coupled like a typical transmission gate. The gate of the NMOS transistor of the transmission switch S1 is connected to the first clock PCLK_M, and the gate of the PMOS transistor of the transmission switch S1 is connected to an output node of an inverter INT for inverting the first clock PCLK_M. Each output node of each transmission switch S1 within the phase delay detectors DDC2-DDCn is connected to an input node of an inversion latch circuit consisting of the inverters I1, I2 and I5 for latching an input signal. If the first clock PCLK_M is logic "HIGH", the delayed clocks D2-Dn generated by the unit delayers FUD1-FUDn are latched to an output node of the inversion latch circuit within the phase delay detectors DCC2-DDCn, and the latched signals are output when respective transmission switches S2 are turned on.
The transmission switch S2, which is switched when the first clock PCLK_M is logic "LOW", is connected to the output node of the inversion latch circuit. A latch circuit consisting of inverters I3 and I4 is connected to an output node of the transmission switch S2 for latching an input delayed clock. The output node Li of the latch circuit is connected to one input of a carry generator consisting of NAND gates N1 and N2 and inverter I6.
The carry generator activates the enable signal at the output node Fi only when the carry input terminal Ti and the output node Ni are logic "HIGH" and "LOW", respectively, and simultaneously disables the carry output terminal Ti+1. For instance, if node T3 is logic "HIGH" and node L3 is logic "LOW", the output of the NAND gate N2 is logic "LOW". Since the output node F3 is logic "LOW", switch SWC3 is turned on. The carry output terminal T4 is logic "LOW" and which disables the carry output. If logic levels which are different from the above example are applied to the nodes T3 and L3, the output node Fi is disabled (logic "HIGH"), and the carry output terminal Ti+1 is enabled (logic "HIGH"). If the enable signal generated at the output node F3 is activated, the first clock PCLK_M is synchronized with delayed clock D3 without any phase delay difference.
In FIG. 4, the delayed clock D12 of the first synchronous delay line is shown synchronized with the first clock PCLK_M. Therefore, output node L12 of the latch circuit of DDC12, as well as the corresponding nodes in DDC13, DDC14, etc., generate logic "LOW". Carry output terminals T13, T14, etc., are disabled. Output node F12 is enabled. Then the delayed clock D12' from the second synchronous delay line passes through a the corresponding switch SWC12 and is provided as the internal clock PCLK through the internal delayer ID.
Although the digital delay locked loop of FIG. 3 can generate an internal clock that is accurately synchronized with the system clock, a large quantity of powers is consumed by the synchronous delay lines and the plurality of phase delay detectors.
Accordingly, a need remains for an improved technique for reducing the skew between the external system clock and the internal clock in a synchronous memory device.